“The MCU is a critical element in the design of many embedded subsystems, but often requires additional functionality to implement the necessary system functions. In an MCU-based design, perhaps one of the most limiting elements is the on-chip memory. More and more applications require more system memory than is available to the MCU. In particular, advanced human-machine interface (HMI) designs may require large amounts of read-only image and audio information that cannot easily be stored in the MCU’s on-chip flash memory. In addition, more and more applications are finding that on-chip RAM is overly limiting for advanced communication channels that require large amounts of data buffering and storage.

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Author: Warren Miller

The MCU is a critical element in the design of many embedded subsystems, but often requires additional functionality to implement the necessary system functions. In an MCU-based design, perhaps one of the most limiting elements is the on-chip memory. More and more applications require more system memory than is available to the MCU. In particular, advanced human-machine interface (HMI) designs may require large amounts of read-only image and audio information that cannot easily be stored in the MCU’s on-chip flash memory. Additionally, more and more applications are finding that on-chip RAM is overly limiting for advanced communication channels that require large amounts of data buffering and storage.

This article will quickly review some of the external memory interfaces available on modern MCUs. This will help designers more efficiently implement MCU-based systems that require additional external storage such as NVM flash or volatile SRAM/DRAM.

External memory interface to SDRAM

Probably the most obvious external memory interface needed to expand storage capacity is large working SRAM. Typically, MCUs have a relatively small amount of on-chip SRAM, and applications often require more working memory than is available on-chip. For example, an advanced user interface may require a large amount of buffer memory to process the graphical user interface (GUI) and create video or audio prompts. Often, compression techniques are used when storing or transferring these data files to reduce local storage requirements or system bandwidth requirements. This means that decompressing these files can require a lot of working storage space. Often, large working memories are also required as buffer memories in communication applications or digital signal processing applications.

Many MCUs provide external memory interface controllers with special circuitry for controlling external SDRAM devices. The NXP LPC1787 is an example MCU microcontroller that highlights the key hardware elements used to support the SDRAM interface. The external memory Controller peripheral, shown in Figure 1, has several programmable delay elements used to adjust the timing of key interface signals used in key SDRAM signals. For example, the delay values ​​of the two potential SDRAM clocks (CLKOUT1 and CLKOUT2) can be adjusted to position transitions according to the memory requirements. Additionally, another programmable delay adjusts when data read from memory is sampled. This timing adjustment, along with its range and accuracy, is critical for simplifying memory interfaces, board layout, and related signal timing checks.

Figure 1: NXP LPC1787 MCU external memory controller. (Courtesy of NXP)

The NXP LPC1787 external memory interface also includes several other important hardware features that make the external SDRAM interface more efficient. For example, the data buffer shown at the top of the block diagram can be used as a read buffer, a write buffer, or a combination. As write buffers, they allow transactions to be grouped to minimize the number of external write operations, increase system bandwidth and reduce power consumption. As read buffers, they act as local copies of data, so further accesses to the same location can use the on-chip buffer version. This reduces the number of external read operations, thereby increasing system bandwidth and reducing power consumption.

Note that NXP memory controllers also support static memory interfaces for RAM, ROM, and Flash. This is the typical approach used in most modern MCU memory controller peripherals, since most of the hardware is common between the two applications, and applications generally do not need to use both types of memory.

Configure external memory

External storage often serves multiple purposes – applications do not see it as a single “block” of storage. A method of configuring blocks of off-chip memory to simplify memory access helps simplify application coding. An example family of MCUs from Silicon Labs C8051F70x/71x that uses this technique. In this MCU, a special MOVX instruction is used to access external memory. To facilitate combined access to on-chip and off-chip memory, a portion of on-chip memory can be mapped into external memory space. Figure 2 shows the four configuration modes available for mapping internal and external memory into the external memory address space. In Mode 1, as shown on the far left of Figure 2, the internal XRAM is mapped to the full external memory space, and addresses “wrap around” when the on-chip XRAM memory address exceeds the amount of on-chip memory. This can be a useful mode when taking the chip out of reset to avoid boot problems with uninitialized external memory. Once the memory interface has been successfully configured and tested, the external memory space can be enabled.

Figure 2: Silicon Labs C8051F70x/71x external memory configuration. (Courtesy of Silicon Labs)

In modes 2 and 3 (second and third from the left in Figure 2), the address space is divided between on-chip and off-chip accesses. In Mode 2, bank select is not used to drive the upper address bits onto the address bus; the user can control these address values ​​for additional flexibility. In Mode 3, the on-chip bank address is automatically used to drive the external address bus, providing a simpler but less flexible method. In Mode 4, on the far right of Figure 2, the off-chip memory is fully mapped into the external address space. This makes it possible to access external data that might otherwise be inaccessible in other addressing modes, in order to fully utilize the available memory. If your application has several different types of external memory requirements – code, data buffers, translation tables,

External memory interface flexibility

In some applications, it is critical that the MCU external memory interface supports multiple memory types while minimizing the device pin count. A common combination is Flash for program storage and SRAM for working memory. If multiple memory interfaces are used on the MCU, this may add 20 or more pins to the package, increasing cost, power consumption, and board space requirements. Some MCUs provide additional flexibility in external memory controllers that can easily accommodate various memory devices. For example, the popular Microchip PIC18FMCU family offers flexible memory interfaces that can be extended to multiple device types. Figure 3 shows one method of interfacing standard flash and standard SRAM with a single external bus. In this case, some external components (two 373 latches and one 138 decoder) are used to minimize the number of pins used on the MCU. (A simpler implementation is also possible for an 8-bit interface that requires only one 373 latch). An external memory interface with this flexibility allows “saved” IO to be used for other functions, maximizing pin efficiency, which is one of the most important elements of an MCU-based design.

Figure 3: Microchip PIC18F MCU external memory interface block diagram. (Provided by Microchip Technology)

Interface Timing Flexibility

In addition to IO interconnect flexibility, external interfaces often require some timing flexibility. For example, if the memory is slower than the MCU clock cycle, a wait state may need to be inserted. Ideally, different blocks of external memory can be assigned different wait-state characteristics. This capability is even more important when the external interface can be used not only for standard memory, but also for memory mapper peripherals such as LCD displays, analog-to-digital converters, and digital-to-analog converters. The Atmel ATmega _MCU family can allocate two different wait state values ​​to the external memory space. As shown in Figure 4 below, memory configuration A allows the external memory to be divided into two sectors – upper and lower. The sector size can have one of eight different values, adjusting the dividing line between the upper and lower segments from 0x2000 to 0xE000 in 0x2000 increments.

Figure 4: Atmel ATmega64 external memory space. (Courtesy of Atmel)

Dividing the external memory space into two sectors makes it easy to combine devices with larger wait-state values ​​and devices with smaller wait-state values. Perhaps most importantly, if zero-wait-state memory is used for frequently accessed program data, zero-wait-state values ​​can be used even if slower devices share the same memory bus. This minimizes MCU pin requirements while increasing performance and saving power.

in conclusion

MCUs sometimes need to expand the available on-chip memory by using an external memory interface. Understanding the capabilities of these interfaces can shorten design time, reduce cost, and improve system performance.