“In recent years, driven by downstream markets such as new energy vehicles, photovoltaics and energy storage, and various power supply applications, silicon carbide power devices have made great progress. Faster switching speed and better temperature characteristics greatly reduce system losses, improve efficiency, and reduce volume, thereby achieving high efficiency and high power density of the converter. However, wide-bandgap (WBG) devices like SiC also present design challenges for application R&D, leading to industry selection and trade-offs for SiC MOSFET planar and trench gates, as well as their inrush current, short-circuit capability, gate There are still doubts about reliability, etc.

“

In recent years, driven by downstream markets such as new energy vehicles, photovoltaics and energy storage, and various power supply applications, silicon carbide power devices have made great progress. Faster switching speed and better temperature characteristics greatly reduce system losses, improve efficiency, and reduce volume, thereby achieving high efficiency and high power density of the converter. However, wide-bandgap (WBG) devices like SiC also present design challenges for application R&D, leading to industry selection and trade-offs for SiC MOSFET planar and trench gates, as well as their inrush current, short-circuit capability, gate There are still doubts about reliability, etc.

How does SiC MOSFET perform?

650V-1200V voltage level SiC MOSFET commercial products have developed from Gen 2 to Gen 3. With the development of technology, the cell width continues to decrease, the specific on-resistance continues to decrease, and the device performance exceeds that of Si devices. Inrush current, short circuit Reliability issues such as capability and gate oxide reliability have attracted much attention. So how much surge current can the SiC MOSFET body diode withstand? What is its short-circuit capability? How to ensure gate reliability?

The magnitude of the surge current resistance of the body diode of a SiC MOSFET is proportional to the size of the chip. For example, Pinjie Semiconductor uses its own 10ms sine half-wave surge limit test platform and 10us square wave half-wave surge limit test platform to sample its 1200V SiC MOSFET P3M12080K3 for 10ms IFSM >120A, 10us IFSM>1100A.

Figure 1 10ms surge limit test platform

Figure 2 10us surge limit test platform

As for the short-circuit capability, compared with Si IGBT, SiC MOSFET has higher current density and thinner gate oxide layer, and its short-circuit capability is weaker than that of Si IGBT, but it still has a certain short-circuit capability.

The following table shows the short-circuit capability of some products of Pinjie semiconductor:

Table 1 Short-circuit withstand capability of 1200V/650V MOSFET devices

The reliability of the gate of Pinjie Semiconductor is strictly in accordance with the AEC-Q101 standard, and the HTGBR and HTRB experiments are carried out at a temperature of 175°C with negative voltage and positive voltage (-4V/+15V) on the gate respectively. No product failure for 1000h. In addition to the 1000h hour experiment required in conventional AEC-Q101, Pincher has done extensive research on gate lifetime. SiC MOSFETs generally have a higher probability of early failure due to the presence of orders of magnitude larger impurity defects at the SiC/SiO2 interface than Si/SiO2. In order to improve the gate reliability of SiC MOSFETs, it is important to identify and isolate early failures through screening. Pinjie Semiconductor established a gate oxide acceleration model through TDDB experiments and established a screening mechanism to eliminate potential failure devices (see previous pushes).

In addition to TDDB, when a normal device is used, the threshold voltage of SiC MOSFET will drift due to the generation of defects or charge and discharge at the semiconductor-oxide interface, and the drift of the threshold voltage may have a significant impact on the long-term operation of the device. Pincher Semiconductor applied a constant DC bias to the SiC MOSFET under high temperature conditions and observed the amount of change in its threshold voltage. Generally, when a forward bias stress is applied, the threshold voltage shifts to a higher voltage; when a negative bias stress is applied, the threshold voltage shifts to a lower voltage. This effect is caused by the carrier trapping at or near the SiC/SiO2 interface. The negative high voltage is the trapping of holes near the MOS interface, resulting in more hole traps; on the contrary, the positive high voltage causes the trapping of electrons. Of course, for some competing products, the threshold voltage shifts to a lower voltage when a forward bias stress is applied; when a negative bias stress is applied, the threshold voltage shifts to a higher voltage. This is caused by the accumulation of mobile ions at the SiC/SiO2 interface. Positive mobile ions accumulate at the SiO2/SiC interface due to positive bias, resulting in a negative shift in threshold voltage; Mobile ions accumulate at the poly/SiO2 interface, causing a positive bias in the threshold voltage. In order to evaluate the threshold voltage drift of the device during use, Pinjie Semiconductor has conducted a large number of BTI experiments, and established a PBTI&NBTI model based on the experimental data. With the help of the model, the threshold voltage drift of the device under different temperatures and gate voltages can be known. Taking the P3M12080K4 product as an example, this product is used in extreme applications (PBTI:V_gs=19V, T_A=150℃) using 20-year threshold voltage drift (+0.348V), the product is under extreme application conditions (NBTI: V_gs=-8V, T_A=150°C) using the 20-year threshold voltage drift (-0.17V).

Advantages and disadvantages of Cascode, plane gate, trench gate

In order to improve the energy efficiency of high-voltage power supply systems, semiconductor manufacturers are actively developing economical and high-performance silicon carbide power devices, such as Cascode structure, silicon carbide MOSFET planar gate structure, silicon carbide MOSFET trench gate structure, etc. What impact do these different technologies have on the application of silicon carbide power devices, and how to choose?

First, Cascode refers to the use of Si MOSFETs and normally-on SiC JFETs connected in series, as shown in Figure 3. When the Si MOSFET gate is high, the MOSFET turns on shorting the GS of the SiC JFET, thus turning it on. When the gate of the Si MOSFET is low, its drain voltage rises until the GS voltage of the SiC JFET reaches the negative voltage at which it is turned off, at which point the device turns off. The main advantage of the Cascode structure is that the same on-resistance has a smaller chip area. Since the gate switch is controlled by the Si MOSFET, the customer can use the Si driver design in the application, and does not need to design the driver circuit separately.

Figure 3 Schematic diagram of SiC Cascode structure

Pinjie Semiconductor believes that the Cascode structure is only a transition product from Si products to SiC products, because the Cascode structure cannot fully exert the unique advantages of SiC devices. First, the high temperature application of Cascode is limited due to the integrated Si MOSFET, especially its high temperature Rdson will reach 2 times that of normal temperature; secondly, the device switching is controlled by Si MOSFET, so the switching frequency is much lower than that of normal SiC MOSFET devices, which is Since the dv/dt of JFET and Si MOSFET can only reach below 10V/ns, the dv/dt of SiC MOSFET can usually reach 30V/ns~80V/ns. These shortcomings make it impossible for Cascode to reduce the size of passive components, so as to reduce the overall system volume and cost; finally, although the Cascode structure uses SiC high-voltage JFET devices to withstand the bus voltage, during the switching process, The output capacitance of the MOSFET and JFET will still divide the voltage. When there is voltage oscillation in the loop, the low-voltage Si MOSFET still has the risk of being broken down.

The main advantage of SiC MOSFET trench gates comes from the vertical channel, which not only improves the carrier mobility (due to the higher mobility of the SiC (1120) plane than the (0001) plane) but also reduces the cell size This results in a lower specific on-resistance than a planar MOSFET. However, because SiC is very hard, the process difficulty and control requirements to obtain a uniform, smooth and vertical etched surface are very high, which is why only Infineon and Rohm have introduced trench gate SiC MOSFETs. The trench gate process not only has very high requirements for process realization, but also has certain risks in terms of reliability. First, the gate oxide quality of the trench gate is at risk due to the limitation of surface roughness and angle after trench etching; secondly, due to the anisotropy of SiC, the thickness of the oxide layer on the sidewall of the trench and the oxide layer at the bottom of the trench are at risk. The thickness is different, so special structures and processes must be used to avoid breakdown at the bottom of the trench, especially at the corners, which also increases the uncertainty of the reliability of the trench gate oxide; finally, due to the structure of the trench MOSFET, the trench The electric field strength of the gate oxide is higher than that of the planar type, which is why Infineon and Rohm do single-sided and double trenches.

SiC MOSFET planar gate is the earliest and most widely used structure, and the current mainstream products use this structure. Pinjie semiconductor products are also used in planar gate MOSFET structure. Based on the planar gate structure, Pinejie has released SiC MOSFETs for various voltage platforms from 650V to 1700V, and has been successfully mass-supplied in leading new energy companies to achieve “on-board”.