The characteristics of Wishbone on-chip bus technology and how to improve the load capacity of the PCI system

Since the advent of the PCI protocol, the PCI bus has become more and more widely used and has become the de facto computer bus standard. With the deepening of PCI applications and development, it is often necessary to use PCI bridges in complex PCI systems to complete design work, including Use the main/PCI bridge to complete the initial configuration process of the entire system. The use of the PCI bridge has been expanded from the traditional PC field to more Electronic application systems.

Since the advent of the PCI protocol, the PCI bus has become more and more widely used and has become the de facto computer bus standard. With the deepening of PCI applications and development, it is often necessary to use PCI bridges in complex PCI systems to complete design work, including Use the main/PCI bridge to complete the initial configuration process of the entire system. The use of the PCI bridge has been expanded from the traditional PC field to more electronic application systems.

1、Introduction to PCI host bridge

In a complex PCI system, there is often more than one PCI bus. In order to improve the load capacity of the PCI system, a PCI-PCI bridge can be used to connect the PCI buses, and a host/PCI bridge is used between the processor bus and the PCI bus. To complete the bus conversion to form a complete PCI system. The commonly used PCI system structure is shown in Figure 1.

The characteristics of Wishbone on-chip bus technology and how to improve the load capacity of the PCI system

When the system is powered on, the initialization of the PCI target device by the main CPU (processor) is also called configuration access. Because the configuration space defined by the PCI target device is usually not in the memory and I/O space of the CPU, a special kind of Mechanism to perform configuration access. This mechanism is usually completed by the main/PCI bridge. The configuration software can scan the PCI bus after power-up to determine which PCI devices are available, and configure them according to their configuration requirements. After the configuration is completed , Each PCI target device can work normally under the coordination and arbitration of the PCI bus controller.

In a PC compatible system, the main/PCI bridge is also called the north bridge, which is used to connect the main processor bus and the basic PCI local bus (first-level PCI bus). The main memory Controller is usually integrated in the north bridge chip, so the processing speed is very high. Fast. The south bridge chip generally integrates IDE controllers, USB and other slower I/O controllers, so the processing speed is relatively slow. The north and south bridges constitute the chipset.

2、Wishbone on-chip bus technology

System-on-chip SOC (System-On-Chip) technology has developed rapidly in the past two years, and more and more manufacturers have begun to develop their own IP cores, and then provide them to system integrators. And each manufacturer adopts their own defined IP core interface specifications to develop Products make system integration a thorny issue. In order to provide the reusability of IP cores and realize the effective interconnection of IP cores from many manufacturers, on-chip bus OCB (On-Chip-Bus) technology came into being. Currently in SOC The three influential on-chip bus standards in the field are: IBM’s Core-connect, ARM’s AMBA, and SilicoreCorp’s Wishbone bus. Among them, the Wishbone bus has been listed as the main supported SOC by the world’s largest Open IP organization (Opencores) Internal interconnection bus protocol. IP cores that follow the Wishbone bus protocol can be quickly and effectively integrated into the SOC. At present, many open IP core interfaces on Opencores use the Wishbone bus design. And more and more IP core commercial vendors also Announced support for Wish-bone bus protocol.

The characteristics of Wishbone on-chip bus technology and how to improve the load capacity of the PCI system

The biggest feature of the Wishbone bus is its simple and flexible structure, requiring fewer logic gates; at the same time, it is completely free and completely open. The Wishbone specification supports a complete common data transmission protocol, including a single read and write cycle, block transmission, etc. The data bus width is 8~64 bits (The width can still be expanded), the address bus can reach 64 bits; the fastest data transmission can be carried out in one clock cycle; support handshake protocol, the rate can be adjusted; support error retry, etc. In the Wishbone bus specification, you can use Master The /Slave structure realizes a very flexible system design. There are four interconnection modes for Master and Slave, namely: point-to-point, data flow, shared bus and cross interconnection. Among them, the point-to-point method is the simplest way to connect a Master and a Slave. It is very convenient to use. Figure 2 shows the Wishbone master/slave interface diagram using point-to-point interconnection. Among them, SYSCON is the module that generates RST reset and CLK clock signals, and TAGN is a user-defined signal.

The handshake protocol used by Wishbone between Master and Slave is shown in Figure 3. When ready to transmit data? Master makes STB O signal valid, STB O state will remain until Slave end signal ACK O, ERR O or RTY O ? For Master, it is ACK I? ERR I and RTY I? One of the statements is valid. Master samples the end signal on every rising edge of CLK I? If the signal is valid? STB O signal goes low. In addition, the Wishbone interface Both sides can fully control the rate of data transfer.

3、PCI Bridge core

The PCI Bridge Core provided by the open IP organization Opencores provides the interface between the Wishbone on-chip system bus and the PCI logic bus. The PCI Bridge Core consists of two relatively independent units: one unit processes data transactions initiated by the PCI bus side, and the other unit Handle transactions initiated by the Wishbone bus party. It is a real bridge between the PCI bus and the Wishbone bus.

The PCI bridge core supports a 32-bit PCI bus interface and is fully compatible with the PCI2.2 protocol (supports 66MHz specifications); it contains an independent host bridge and slave bridge function modules and a complete command/status register; supports Wishbone SOC interconnection protocol version B (Including B1 and B3); In addition, it can support 32-bit bus operation through the Wishbone interface; on-chip FIFO can be configured.

3.1 Internal structure of PCI Bridge

The PCI bridge core is composed of two relatively independent unit modules: the PCI target unit and the Wishbone slave unit. Each unit has a complete set of functions to support transactions between Wishbone and the PCI bus. The Wishbone slave unit can be used as a PCI bridge The slave device on the Wish-bone side and the master device on the PCI side initiate transactions; the PCI target unit can be used as the target device on the PCI side of the PCI bridge and the master device on the Wishbone side to initiate transactions. The two units are independent of each other. The PCI target unit is used Implement PCI bus slave interface and Wishbone bus master interface; Wishbone slave unit is used to implement Wishbone bus slave interface and PCI bus master interface.

The characteristics of Wishbone on-chip bus technology and how to improve the load capacity of the PCI system

Figure 4 shows the internal structure of the PCI bridge core.

3.2 PCI Bridge operation

The PCI bridge core has two application methods: master and slave bridge (relative to the PCI bus). As a slave bridge, when the PCI bridge is connected to the host system with the PCI bus and powered on, the host system software will scan the connection on the PCI bus PCI bus device (including PCI bridge), and then configure the PCI bridge space register, that is, the configuration software completes the initial configuration process of the PCI bridge. After that, the PCI bridge enters the normal working state.

When the PCI bridge core is used as the host bridge, the PCI bridge fully controls the PCI bus. The Wishbone proxy device of the PCI bridge is fully responsible for the initial configuration process of the PCI devices connected to the PCI bus. The firmware (device independent software) running on the Wishbone proxy device is in Scan the PCI bus after power-on to determine which PCI devices are there and what configuration requirements are there. Then configure the configuration space of each PCI device in the Wishbone image 0 space. After the configuration is completed, you can load the driver of each PCI device. This PCI devices can also access the Wishbone bus through the PCI target unit of the PCI bridge.

The configuration space of the PCI bridge includes two parts: one part is the configuration, status and control registers of the Wishbone slave unit; the other part is the configuration, status and control registers of the PCI target unit (including the 256-byte standard configuration required by the PCI protocol Space). The PCI bridge implements the proxy devices on both sides of the PCI bridge to access the configuration space of the PCI bridge through the corresponding address image space (PCI image 0 and Wishbone image 0). As a slave bridge, the host bridge of the host system can use ordinary memory Read and write instructions to access the configuration space of the PCI bridge. You can also access the lower 256 bytes of the PCI bridge configuration space by configuring read and write instructions. When used as a host bridge, the PCI bridge itself can generate a configuration cycle. Just like the PC X86 system The host bridge configuration mechanism is the same as 0, the Wishbone proxy host device of the PCI bridge can generate configuration read and write commands by accessing the CNF_ADDR and CNF_DATA registers of the PCI bridge configuration space, thereby realizing the power-on initialization process of other PCI devices.

The characteristics of Wishbone on-chip bus technology and how to improve the load capacity of the PCI system

Since the PCI bridge core is a soft core, there is a parameter header file in the PCI bridge core. The operation mode of the PCI bridge can be changed by changing the parameters of the PCI bridge core header file (such as host bridge or slave bridge settings, PCI or Wishbone image The definition of space, etc.), so it is very convenient to use.

4、 Use PCI Bridge core to access PCI devices

The PCI bridge is generally used as a slave bridge on PCI expansion cards (or PCI peripheral cards), such as data acquisition, image transmission, etc., and as a host bridge is generally used on the main control board of the PCI bus (or PCI system card), But it is necessary to initialize the functional devices on the PCI bus and control the operation of the PCI bus.

In order to debug the application of the master/slave bridge, the author designed three circuit boards to coordinate and control the operation of the PCI bus. One is an FPGA board (Xilinx’s Spartan II chip, designed with a PCI interface), and one is a microcontroller board (51 MCU), one is a common PCI expansion card.

As a slave bridge, you only need an FPGA board to complete the entire experimental process. That is, use Verilog language to implement a Wishbone slave interface and connect it to the BlockRAM inside the FPGA (generated by the CORE generator of ISE), and then select the application of the PCI Bridge core The mode is GUEST (slave bridge mode), and compile and download it to the FPGA configuration chip along with its own program. In this way, insert the FP-GA board into the PCI slot of the PC, and then you can develop a driver on the PC to access the FPGA The resources on the board (such as RAM, etc.). If you want to collect data, you can connect Wishbone from the interface to the data collection module. The functional module diagram realized from the bridge is shown in Figure 5.

When used as a host bridge (the application method of the PCI Bridge core is HOST), because there is no microcontroller on the FPGA board, it is necessary to connect the I/O port on the FPGA board with the I/O expansion port on the 51 single-chip circuit board The PCI main control board is formed together. The FPGA board and the ordinary PCI expansion board are inserted into the PCI slots of the independent PCI backplane, and then the FPGA board and the microcontroller board are programmed to realize the initial configuration and normalization of the ordinary PCI expansion board Read and write operations. The block diagram of the circuit function module is shown in Figure 6.

The characteristics of Wishbone on-chip bus technology and how to improve the load capacity of the PCI system

Since the interface of the microcontroller is 8-bit, the read and write timing is also different from the Wishbone timing in the PCI bridge, so it is necessary to use software to implement a Wishbone main interface between the PCI bridge and the microcontroller expansion I/O port. The working process of the Wishbone main interface It is: when the single-chip microcomputer sends out a read operation, the 8-bit address data is first transmitted 4 times to the FPGA, and then the 32-bit address composed of the Wishbone main interface is stored in a 32-bit address register, and then the single-chip microcomputer sends a read command to start the Wishbone main interface Perform the read timing of the Wishbone bus. When the Wishbone main interface stores the 32-bit data read from the PCI bus in a 32-bit read data register, the single-chip microcomputer will read the 32-bit data in 4 times; the single-chip write operation is like a read Similarly, the 32-bit address and 32-bit data are transmitted in turn, and finally the write command is sent to start the Wishbone main interface to perform the write timing of the Wishbone bus. The read and write timing of Wishbone can be implemented by the synchronization state machine described in the Verilog language.

The complete software process of using C language programming to realize the firmware of the main control board on the 51 single-chip microcomputer is: After power-on, the firmware first scans the PCI devices existing on the PCI bus in order. One of the purposes of scanning is to number the bus and the device. After the scan, the device type, topological location and other information are stored in a data structure based on the device, and a linked list is formed in the order of the actual scan. At the same time, the configuration requirements of the device are also stored in this data linked list in turn. The firmware is obtained After the device topology of the system, configure them one by one according to the configuration requirements of the device, that is, allocate address resources to the base address register of the device. After the configuration is completed, each PCI device can enter the normal working state.

The Links:   NL10276BC30-33D LT104AD18F00

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