The wayward DDR2 design for everyone to find the fault (Part 1)

As mentioned earlier, designers did not notice that the DDR3 main control does not have a read-write balance function, so they routed them according to the conventional wiring requirements, resulting in a large difference in the length of the data and clock signals, and ultimately making the DDR3 system run less than the rated frequency. It seems that there is no DDR3 with balanced reading and writing. It is more reliable to follow the design rules of DDR2 directly. So what are the rules for the design of DDR2? I think everyone will be more interested.

As mentioned earlier, designers did not notice that the DDR3 main control does not have a read-write balance function, so they routed them according to the conventional wiring requirements, resulting in a large difference in the length of the data and clock signals, and ultimately making the DDR3 system run less than the rated frequency. It seems that there is no DDR3 with balanced reading and writing. It is more reliable to follow the design rules of DDR2 directly. So what are the rules for the design of DDR2? I think everyone will be more interested.

What are the rules? The so-called practice leads to truth, let’s take a look at the following case first!

This DDR2 system adopts the design of 8 particles on the bottom of the table, the address, control, and command signals are dragged by eight, and the other signals are dragged by two, but the final system cannot run. Check the PCB design, the screenshots of some of the signals are listed below, don’t comment first, everyone slowly start to find the fault.

The wayward DDR2 design for everyone to find the fault (Part 1)

The highlighted part in the above figure is the trace of the clock signal (green and white). From the main control chip, change the layer and pass through 1300mil to the branch via. Here, a 100ohm differential impedance is terminated, and then a section of 1250mil and 1250mil is branched from the via. The 1350 mil trace goes to the two particles at the bottom of the table, and one of the particles is terminated with a 100 ohm differential resistor. The other clock signals are also roughly the same.

The wayward DDR2 design for everyone to find the fault (Part 1)

The yellow highlighted part in the figure is the address signal routing. The first level branch is immediately after coming out of the main control chip, and then about 600mil for the second level branch, another branch passes through 1000mil for the third level branch, and the other branch is about 50mil. Start the third-level branch, and finally connect a 0ohm series resistance of about 1100mil to the particles, in which a 47ohm resistor is pulled up to Vtt at a third branch via on the most side, and other address and control signals are roughly the same structure.

The wayward DDR2 design for everyone to find the fault (Part 1)

Let’s look at the DQS signal again. As shown in the figure above, the rose red and white dot signal is highlighted. After the first-level branch, each 0ohm series resistance passes through the 350mil and 738mil lines to the surface and bottom particles. The other differences are not big.

The wayward DDR2 design for everyone to find the fault (Part 1)

Finally, look at the data signal. The yellow highlighted part in the figure uses a daisy chain structure, first to one of the particles, and then to the second particle on the other side. The other data signals also have this structure.

Well, we don’t need to look at other things like power supply. We already know that there is a reason why the DDR2 system can’t run.

The Links:   00-168-334 MDC100-16 IGBTS

Related Posts

Leave a Reply

Your email address will not be published. Required fields are marked *